Charge amplification by means of an operational amplifier with inverse feedback via a capacitor is used in many readout applications, such as for example voltage readout, capacitor readout or charge packet readout.
As is known per se, an operational amplifier has a limited voltage gain in the defined range of its supply voltages. The gain is further limited to a range of frequencies, with the amplifier usually having a gain of the low-pass type. Moreover, this frequency range depends on the impedance of the charges connected at the amplifier input and output, charges which therefore have an effect on the time taken to establish the amplified signal at the amplifier output.
To overcome these drawbacks, an impedance is conventionally mounted in inverse feedback between the inverting input and the output of the amplifier, in such a way that the transfer function of the system so looped does not depend predominantly on this impedance.
When the inverse feedback impedance is a capacitor, we then talk about charge amplification. Indeed, an operational amplifier with inverse feedback via a capacitor amplifies the charges it receives at input.
FIG. 1 shows a prior art device for converting charge into voltage 10. This amplification device 10 is connected at input to an input stage 12 and at output to an output stage 14.
The conversion device 10 includes an operational amplifier 16, of transconductance gm, and an inverse feedback capacitor 18, of value Cfb, connected between the inverting terminal 20 and the output terminal 22 thereof. The non-inverting terminal 24 of the amplifier 16 is for its part connected to a reference potential, such as an earth 26 for example.
The input stage 12 comprises a voltage source 28, connected between the earth 26 and a terminal 30 and of value Ve, and a voltage conversion capacitor 32, connected between the terminals 30 and 31, of value Cmes.
The output stage 14 comprises for its part an input equivalent capacitor 34 of value Cout and connected between the output terminal 22 of the amplifier 16 and the earth 26.
In the diagram in FIG. 1, parasitic capacitors 36, 38, 40 are also shown. These capacitors are generated by the structure of the transistors, of MOS technology for example, that constitute the amplifier 16, and by the various interconnections (tracks, wires, metal solders, etc.) which exist in, and between, the different elements that have just been described.
Conventionally, these parasitic capacitors 36, 38, 40 are modeled by:                an input parasitic capacitor 36 of the amplifier 16 of value Cpin. This parasitic capacitor 36 is connected between the inverting terminal 20 thereof and the earth 26;        an output parasitic capacitor 38 of the amplifier 16 of value Cpout. This parasitic capacitor 38 is connected between the output terminal thereof and the earth 26; and        a parasitic capacitor 40 of the input stage connections, of value Cis. This parasitic capacitor 40 is connected in parallel to the input parasitic capacitor 36 of the amplifier.        
Controllable circuit breakers 42, 44, 46, 48, 50, 52 are also provided, a first circuit breaker 42 being connected in parallel to the inverse feedback capacitor 18, a second circuit breaker 44 being connected at the input of the amplifier 16 between the inverting terminal 20 and the terminal 31 of the capacitor 32 of the input stage 12, a third circuit breaker 46 being connected between this capacitor 32 and the voltage source 28, a fourth circuit breaker 48 being connected between the terminal 30 of the input stage and the earth 26, a fifth circuit breaker 50 being connected between the terminal 31 of the input stage and the earth 26, and a sixth circuit breaker 52 being connected between the output 22 of the amplifier 16 and the input equivalent capacitor 34 of the output stage 14.
The circuit breakers 42, 44, 46, 48, 50, 52 are controlled by a generator 70 of two control signals φ1, φ2 in accordance with a strategy for switching on and off as described hereinafter, the signal φ1 controlling the switching on and off of the circuit breakers 42, 48 and 50, and the signal φ2 controlling the switching on and off of the circuit breakers 44, 46 and 52.
Depending on the nature of the circuit breakers, the generator 70 may possibly be led to deliver signals that are complementary in terms of binary logic, particularly in respect of controlling CMOS circuit breakers.
FIG. 1, for example, shows amplification of the voltage Ve by means of charge amplification.
Initially, the first, fourth and fifth circuit breakers 42, 48 and 50 are off and the second, third and sixth circuit breakers 44, 46, 52 are on. The inverse feedback capacitors 18 and voltage conversion capacitors 32 are therefore discharged.
Secondly, the first, fourth and fifth circuit breakers 42, 48 and 50 are on and the second, third and sixth circuit breakers 44, 46, 52 are off. The voltage Ve at the terminals of the source 28 is thus converted into a charge Qe by the voltage conversion capacitor 32, and an equivalent charge Qe′ (=Qe) is generated at the terminals of the inverse feedback capacitor 18 by conserving the charge at the non-inverting input 20 of the amplifier 16. This charge Qe′ is converted into voltage Vout by means of the inverse feedback capacitor 18. This voltage Vout can be observed at the terminals of the capacitors Cpout 38 and Cout 34.
The transfer function between amplified voltage Vout and the voltage Ve is thus given by the following formula:
                              G          ⁡                      (            s            )                          =                                            C              mes                        ⁢                                          R                out                            ⁡                              (                                                      -                                          g                      m                                                        +                                                            C                      fb                                        ⁢                    s                                                  )                                                                                                                                                    (                                                                        C                          mes                                                +                                                  C                          is                                                +                                                  C                          pin                                                                    )                                        ⁢                                          (                                              1                        +                                                                              (                                                                                          C                                out                                                            +                                                              C                                pout                                                                                      )                                                    ⁢                                                      R                            out                                                    ⁢                          s                                                                    )                                                        +                                                                                                                          C                    fb                                    ⁡                                      (                                          1                      +                                                                                                    R                            out                                                    ⁡                                                      (                                                                                          C                                mes                                                            +                                                              C                                out                                                            +                                                              C                                pout                                                            +                                                              C                                pin                                                            +                                                              C                                is                                                                                      )                                                                          ⁢                        s                                                              )                                                                                                          (        1        )            where s is the Laplace variable and Rout the output impedance of the operational amplifier 16.
The transfer function G(s) is therefore of the first order low-pass type.
The continuous gain G0 of the function G(s) is given by the formula:
                              G          0                =                  -                                                    C                mes                            ⁢                              g                m                            ⁢                              R                out                                                                    C                mes                            +                              C                pin                            +                              C                is                            +                                                C                  fb                                ⁡                                  (                                      1                    +                                                                  g                        m                                            ⁢                                              R                        out                                                                              )                                                                                        (        2        )            
The cutoff frequency ωc is furthermore equal to:
                              ω          c                =                              g            m                                C            eq                                              (        3        )            where Ceq is a capacitor according to the formula:
                              C          eq                =                                                                                                                        (                                                                        C                          pout                                                +                                                  C                          out                                                                    )                                        ⁢                                          (                                                                        C                          mes                                                +                                                  C                          pin                                                +                                                  C                          is                                                                    )                                                        +                                                                                                                          C                    fb                                    ⁡                                      (                                                                  C                        pout                                            +                                              C                        out                                            +                                              C                        mes                                            +                                              C                        pin                                            +                                              C                        is                                                              )                                                                                            C            fb                                              (        4        )            
It will be noted that the capacitor Ceq may be rewritten according to the formula:
                              C          eq                =                                                            C                S                            ⁢                              C                E                                      +                                          C                fb                            ⁡                              (                                                      C                    S                                    +                                      C                    E                                                  )                                                          C            fb                                              (        5        )            where CE=Cmes+Cpin+Cis is the capacitor seen at input by the amplifier 16 and CS=Cpout+Cout is the capacitor seen at output by the amplifier 16.
It can thus be seen from a consideration of the formulae (2) and (3) that to increase the amplification passband and therefore the speed thereof (the higher the cutoff pulsatance ωc the shorter the amplifier output signal establishment time), ωc needs to be maximized.
To do this, it is possible to minimize the equivalent capacitance Ceq or to maximize the transconductance gm of the amplifier 16.
However, increasing the transconductance gm involves using a high-energy consuming amplifier. Additionally, increasing the transconductance gm also results, in respect of the amplifier, in a transistor geometry with larger parasitic capacitors Cpin and Cpout. The equivalent capacitance Ceq is then larger and the cutoff pulsatance ωc smaller.
The passband may also be increased by minimizing the equivalent capacitance Ceq.
To lower the value thereof, it is possible to maximize the value of the inverse feedback capacitor Cfb. In fact, maximizing Cfb has the effect of reducing the continuous gain G0, which runs counter to the primary intended aim, namely amplification.
That is why, passband maximization is usually sought and obtained by minimizing the parasitic capacitors Cpin and Cpout. Research has thus been carried out on the structure and geometry of the transistors constituting the amplifier 16. Said research is however long and complex in so far as it relates to transistor design.
Furthermore, even though the parasitic capacitors might be optimized, the equivalent capacitance Ceq still depends on the input 12 and output 14 stages, and particularly on the capacitors Cmes, Cis and Cout. The passband gain, and therefore the establishment time gain, is limited by the presence of these capacitors. Likewise, there are still parasitic capacitors at the amplifier input and output which are not connected to the amplifier itself. The parasitic capacitors of the connections of the amplifier 16 with the input 12 and output 14 stages may be cited in particular.
It will be noted that the problems disclosed above are posed in the same way in other charge amplification applications. For example, it will also be noted that FIG. 1 shows the readout of the value Cmes of the capacitor 32 whereof the value is unknown.
In such an application the value of the voltage Ve is known and the voltage Vout at the terminals of the charge conversion capacitor 34 measured. The transfer function between the voltage Vout and the capacitor Cmes is then given by the formula:
                              G          0                =                                            V              e                        ⁢                          g              m                        ⁢                          R              out                                                          C              mes                        +                          C              pin                        +                          C              is                        +                                          C                fb                            ⁡                              (                                  1                  +                                                            g                      m                                        ⁢                                          R                      out                                                                      )                                                                        (                  2          ⁢          C                )            
This transfer function is also of the lowpass type with cutoff pulsatance similar to that in the formula (3). Said application is for example described in the document by N. Yazdi et al. “Precision readout circuits for capacitive microaccelerometers”, Sensors 2004, Proceedings of IREE.
It will be noted that said application generally comprises measuring the variations in the voltage conversion capacitor 32 (Cmes) around a reference value that is much higher than said variations. This involves in particular choosing the inverse feedback capacitor 18 to be of the same order of magnitude as the variations in the capacitor 32, so that the equivalent capacitance is substantially equal to
      C    eq    =                              C          S                ⁢                  C          E                            C        fb              .  The influence of the parasitic capacitors on the amplification passband is therefore strengthened as a result.
These problems are also posed in the case of voltage conversion of charge packets from a plurality of input stages sharing a single conversion device. The input stages are for example the pixels of a column of a matrix sensor such as a CCD or CMOS image sensor, which periodically delivers charge packets for conversion into voltage on a column bus.
In a similar way to the aforementioned applications, the transfer function between the voltage Vout and a received charge packet Qe is of the low-pass type according to the formula:
                              G          0                =                                            g              m                        ⁢                          R              out                                                          C              mes                        +                          C              pin                        +                          C              is                        +                                          C                fb                            ⁡                              (                                  1                  +                                                            g                      m                                        ⁢                                          R                      out                                                                      )                                                                        (                  2          ⁢          Q                )            
The cutoff pulsatance of this transfer function is therefore similar to that of the formula (3). It will be noted that in this application, the parasitic capacitor connected to the column bus connection is very large, thereby limiting the voltage conversion passband of the incident charge packets.
The aim of the invention is to resolve the abovementioned problem by proposing a method for controlling the conversion device which allows a significant gain in passband, and therefore in establishment time, and does so by modifying at least the structure, the operation or the arrangement of the amplifier or of the input and output stages, and without getting a reduction in the final conversion gain.